Core Research Areas
VLSI-Digital Architecture; Mixed-Signal Circuit & System; ASIC-Chip Tape-out & Testing.
System Level Design and FPGA Prototyping/Emulation.
Digital Signal Processing & Wirless Communication.
Spectrum Sensing for Cognitive Radio Application.
Channel Decoders for Next Generation (4G/5G-NR and beyond) of Wireless Communication Systems.
Welcome
"Purity, patience, and perseverance are the three essentials to success, and above all, love." - Swami Vivekananda.
I heartily welcome all to my personal web page. Presently, I hold a position of Associate Professor in the School of Computing & Electrical Engineering (SCEE), Indian Institute Technology (IIT) Mandi. I graduated from B. M. S. College of Engineering Bangalore, as Telecommunication Engineer in the year 2008 and accomplished my Doctoral Study (PhD Thesis) from the Indian Institute of Technology Guwahati (IITG) in the year 2014.
Contact Details
Chip Gallery
Chip-1: A Multiple Radix Maximum A-Posteriori (MAP) Decoder ASIC Chip, Fabricated in UMC 130 nm-CMOS Technology Node, for Energy Efficient and Variable Throughput Applications.
Published in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, October 2020.
Chip-2: New Cooperative Spectrum-Sensors for Cognitive Radio Network, Fabricated in UMC 130 nm-CMOS Technology Node.
Published in IEEE Transactions on Consumer Electronics, Apr. 2022.
Published in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Feb. 2022.
Chip-3:An ASIC Chip of Reconfigurable LDPC/Polar Decoder for mMTC and URLLC 5G-NR Applications, Fabricated in UMC 110 nm-CMOS Technology Node.
Published in IEEE Transactions on Circuits and Systems--I: Regular Papers, July 2024.