List of Publications

Journal Publications

Anuj Verma and Rahul Shrestha, “High-Throughput and Hardware-Efficient ASIC-Chip Fabrication of Reconfigurable LDPC/Polar Decoder for mMTC and URLLC 5G-NR Applications,” IEEE Transactions on Circuits and Systems I: Regular Papers, DOI: 10.1109/TCSI.2024.3429174, Volume: 71, Issue: 9, pp. 4284-4297, September-2024, web link.

Md. Najrul Islam, Rahul Shrestha, and Shubhajit Roy Chowdhury, “Energy-Efficient and High-Throughput CNN Inference Engine Based on Memory-Sharing and Data-Reusing for Edge Applications,” IEEE Transactions on Circuits and Systems I: Regular Papers, DOI: 10.1109/TCSI.2024.3392807, Volume: 71, Issue: 7, pp. 3189-3202, July-2024, web link.

Elivander J. T. Pereira, Dayan A. Guimaraes, and Rahul Shrestha, “VLSI Architectures and Hardware Implementation of Ultra Low-Latency and Area-Efficient Pietra-Ricci Index Detector for Spectrum Sensing,” IEEE Transactions on Circuits and Systems I: Regular Papers, DOI:10.1109/TCSI.2024.3376952, Volume: 71, Issue: 5, pp. 2348-2361, May-2024 web link.

Shakti Singh and Rahul Shrestha, “Ultra-Low Sensing-Time and Hardware-Efficient Spectrum Sensor for Data Fusion based Cooperative Cognitive-Radio Network,” IEEE Transactions on Consumer Electronics, DOI:10.1109/TCE.2023.3322831, Volume: 70, Issue: 1, pp. 216-26, February-2024, web link.

Shakti Singh and Rahul Shrestha, “A New Hardware-Efficient and Low Sensing-Time Cooperative Spectrum-Sensor for High-Throughput Cognitive-Radio Network,” IEEE Transactions on Circuits and Systems I: Regular Papers, DOI:10.1109/TCSI.2023.3331439, Volume: 71, Issue: 1, pp. 262-273, January-2024, web link.

Dayan A. Guimaraes, Elivander J. T. Pereira, and Rahul Shrestha, “Resource-Efficient Low-Latency Modified Pietra-Ricci Index Detector for Spectrum Sensing in Cognitive Radio Networks,” IEEE Transactions on Vehicular Technology, DOI: 10.1109/TVT.2023.3269345, Volume: 72, Issue: 9, pp. 11898-11912, September-2023, web link.

Rahul Sharma, Rahul Shrestha, and Satinder Kumar Sharma, “Hardware-Efficient and Short Sensing-Time Multicoset-Sampling Based Wideband Spectrum Sensor for Cognitive Radio Network,” IEEE Transactions on Circuits and Systems I: Regular Papers, DOI: 10.1109/TCSI.2022.3223356, Volume: 70, Issue: 3, pp. 1298-1310, March-2023, web link.

Anuj Verma and Rahul Shrestha, “Low Computational-Complexity SOMS-Algorithm and High-Throughput Decoder Architecture for QC-LDPC Codes,” IEEE Transactions on Vehicular Technology, DOI: 10.1109/TVT.2022.3203802, Volume: 72, Issue: 1, pp. 66-80, January-2023, web link.

Md. Najrul Islam, Rahul Shrestha, and Shubhajit Roy Chowdhury, “An Uninterrupted Processing Technique Based High-Throughput and Energy-Efficient Hardware Accelerator for Convolutional Neural Networks,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, DOI: 10.1109/TVLSI.2022.3210963, Volume: 30, Issue: 12, pp. 1891-1901, December-2022, web link.

Lalit Kumar and Rahul Shrestha, “A System-Level Design & Implementation for Real-Time Interception & Monitoring the Frequency-Agile Communication Signal,” Journal of Signal Processing Systems - Springer Nature, DOI: 10.1007/s11265-022-01810-2, Available Online, September-2022, web link.

Sumanth Gudaparthi and Rahul Shrestha, “Selective Register-File Cache: An Energy Saving Technique for Embedded Processor Architecture,” Journal of Design Automation for Embedded Systems - Springer Nature, DOI: 10.1007/s10617-022-09264-2, Available Online, May-2022, web link.

Rahul Sharma, Rahul Shrestha, and Satinder Kumar Sharma, “Low-Latency and Reconfigurable VLSI-Architectures for Computing Eigenvalues and Eigenvectors Using CORDIC-Based Parallel Jacobi Method,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, DOI: 10.1109/TVLSI.2022.3170526, Volume: 30, Issue: 8, pp. 1020-1033, August-2022, web link.

Rohit B. Chaurasiya and Rahul Shrestha, “Design and ASIC-Implementation of Hardware-Efficient Cooperative Spectrum-Sensor for Data Fusion Based Cognitive Radio Network,” IEEE Transactions on Consumer Electronics, Volume: 68, Issue: 3, pp. 221-235, August-2022, web link.

Rohit B. Chaurasiya and Rahul Shrestha, “Hardware-Efficient VLSI-Architecture and ASIC-Implementation of GRCR based Cooperative Spectrum Sensor for Cognitive-Radio Network,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume: 30, Issue: 2, pp. 166-176, February-2022, web link.

Anuj Verma and Rahul Shrestha, “Hardware-Efficient and High-Throughput LLRC Segregation Based Binary QC-LDPC Decoding Algorithm and Architecture,” IEEE Transactions on Circuits and Systems II: Express Briefs, Volume: 68, Issue: 8, pp. 2835-2839, August-2021, web link.

Rohit B. Chaurasiya and Rahul Shrestha, “Area-Efficient and Scalable Data-Fusion based Cooperative Spectrum Sensor for Cognitive Radio,” IEEE Transactions on Circuits and Systems II: Express Briefs, Volume: 68, Issue: 4, pp. 1198-1202, April-2021, web link.

Rohit B. Chaurasiya and Rahul Shrestha, “A New Hardware-Efficient Spectrum-Sensor VLSI-Architecture for Data Fusion based Cooperative Cognitive-Radio Network,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume: 29, Issue: 4, pp. 760-773, February-2021, web link.

Rahul Shrestha, “A Multiple-Radix MAP-Decoder Microarchitecture and its ASIC Implementation for Energy-Efficient and Variable-Throughput Applications,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume: 29, Issue: 1, pp. 65-75, January-2021, web link.

Rohit B. Chaurasiya and Rahul Shrestha, “Fast Sensing-Time and Hardware-Efficient Eigenvalue based Blind Spectrum Sensors for Cognitive Radio Network,” IEEE Transactions on Circuits and Systems I: Regular Papers, Volume: 67, Issue: 4, pp. 1296-1308, April-2020, web link.

Rohit B. Chaurasiya and Rahul Shrestha, “Hardware-Efficient and Fast Sensing-Time Maximum-Minimum-Eigenvalue based Spectrum Sensor for Cognitive Radio Network,” IEEE Transactions on Circuits and Systems I: Regular Papers, Volume: 66, Issue: 11, pp. 4448-4461, November-2019, web link.

Rahul Shrestha and Abhijit Sahoo, “High-Speed and Hardware-Efficient Successive Cancellation Polar-Decoder,” IEEE Transactions on Circuits and Systems II: Express Briefs, Volume: 66, Issue: 7, pp. 1144-1148, October-2019, web link.

Mahesh S. Murty and Rahul Shrestha, “Reconfigurable & Memory-Efficient Cyclostationary Spectrum Sensor for Cognitive-Radio Wireless Networks,” IEEE Transactions on Circuits and Systems II: Express Briefs, Volume: 65, Issue: 8, pp. 1039-1043, August-2018, web link.

Mahesh S. Murty and Rahul Shrestha, “Hardware Implementation and VLSI Design of Spectrum Sensor for Next-Generation LTE-A Cognitive-Radio Wireless-Network,” IET Circuits, Devices and Systems, Volume: 12, Issue: 5, pp. 542-550, August-2018, web link.

Naman Govil, Rahul Shrestha and Shubhajit Roy Chowdhury, “PGMA: An Algorithmic Approach for Multi-objective Hardware Software Partitioning,” Journal of Microprocessors and Microsystems: Embedded Hardware Design (MICPRO) - Elsevier, Volume: 54, pp. 83-96, October-2017, web link.

Rahul Shrestha and Roy Paily, “Memory-Reduced Maximum-A-Posteriori-Probability Decoding for High-Throughput Parallel-Turbo Decoders,” Journal of Circuits, Systems, and Signal Processing - Springer, Volume: 35, Issue: 8, pp. 2832-2854, August-2016, web link.

Vijaya Kumar K, Rahul Shrestha and Roy Paily, “Multi-Standard High-Throughput and Low-Power QC-LDPC Decoder for WiMAX and WiFi Standards,” IET Circuits, Devices and Systems, Volume: 10, Issue: 2, pp. 111-120, Mach-2016, web link.

Rahul Shrestha and Roy Paily, “VLSI Design and Hardware Implementation of High-Speed Energy-Efficient Logarithmic-MAP Decoder,” Journal of Low Power Electronics, Volume: 11, Issue: 3, pp. 406-412, September-2015, web link.

Sachin Kumawat, Rahul Shrestha, Nikunj Daga and Roy Paily, “High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule,” IEEE Transactions on Circuits and Systems I: Regular Papers, Volume: 62, Issue: 5, pp. 1421-1430, May-2015, web link.

Rahul Shrestha and Roy Paily, “High-Throughput Turbo Decoder with Parallel Architecture for LTE Wireless Communication Standards,” IEEE Transactions on Circuits and Systems I: Regular Papers, Volume: 61, Issue: 9, pp. 2699-2710, September-2014, web link.

Rahul Shrestha and Roy Paily, “Comparative Study of Simplified MAP Algorithms and an Implementation of Non-Parallel-Radix-2 Turbo Decoder,” Journal of Signal Processing Systems - Springer, Volume: 81, Issue: 2, pp. 305-320, September-2014, web link.

Rahul Shrestha and Roy Paily, “Performance and Throughput Analysis of Turbo Decoder for the Physical Layer of Digital Video Broadcasting - Satellite-services to Handhelds (DVB-SH) Standard,” IET Communications, Volume: 7, Issue: 12, pp. 1211-1220, 2013, web link.

Rahul Shrestha and Roy Paily, “Design and Implementation of a Linear Feedback Shift Register Interleaver for Turbo Decoding,” Springer Berlin/Heidelberg Lecture Notes in Computer Science, Volume: 7373, pp. 30-39, 2012, web link.

Conference Publications

Md. Najrul Islam, Rahul Shrestha and Shubhajit Roy Chowdhury, “Low-Complexity Classification Technique and Hardware-Efficient Classify-Unit Architecture for CNN Accelerator ,” 37th IEEE International Conference on VLSI Design and 23rd International Conference on Embedded Systems (VLSID), pp. 210-215 (DOI: 10.1109/VLSID60093.2024.00041), January-2024, Kolkata (India), web link.

Meghvern Pathak and Rahul Shrestha, “Hardware Architecture and FPGA Implementation of Low Latency Turbo Encoder for Deep-Space Communication Systems,” 36th IEEE International Conference on VLSI Design and 22nd International Conference on Embedded Systems (VLSID), pp. 1-6 (DOI: 10.1109/VLSID57277.2023.00016), January-2023, India (Hyderabad) web link.

Kumari Suravi and Rahul Shrestha, “High-Throughput VLSI Architecture for LDPC Decoder Based on Low-Latency Decoding Technique for Wireless Communication Systems,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 206-211 (DOI: 10.1109/ISVLSI54635.2022.00048), July-2022, Cyprus (Nicosia), web link.

Md. Najrul Islam, Rahul Shrestha and Shubhajit Roy Chowdhury, “A New Hardware-Efficient VLSI-Architecture of GoogLeNet CNN-Model Based Hardware Accelerator for Edge Computing Applications,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 414-417 (DOI: 10.1109/ISVLSI54635.2022.00093), July-2022, Cyprus (Nicosia), web link.

Rohit B. Chaurasiya and Rahul Shrestha, “Hardware-Efficient ASIC Implementation of Eigenvalue Based Spectrum Sensor Reconfigurable-Architecture for Cooperative Cognitive-Radio Network,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5 (DOI: 10.1109/ISCAS51556.2021.9401570), May-2021, South Korea (Daegu), web link.

Rahul Shrestha and Shubham Telgote, “A Short Sensing-Time Cyclostationary Feature Detection Based Spectrum Sensor for Cognitive Radio Network,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5 (DOI: 10.1109/ISCAS45731.2020.9180415), Oct-2020, Spain (Seville), web link.

Anuj Verma and Rahul Shrestha, “A New VLSI Architecture of Next-Generation QC-LDPC Decoder for 5G New-Radio Wireless-Communication Standard,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5 (DOI: 10.1109/ISCAS45731.2020.9181188), Oct-2020, Spain (Seville), web link.

Anuj Verma and Rahul Shrestha, “A New Partially-Parallel VLSI-Architecture of Quasi-Cyclic LDPC Decoder for 5G New-Radio,” 33rd IEEE International Conference on VLSI Design and 19th International Conference on Embedded Systems (VLSID), pp. 1-5 (DOI: 10.1109/VLSID49098.2020.00018), Jan-2020, India (Bangalore), web link.

Rohit B. Chaurasiya and Rahul Shrestha, “Hardware-Efficient and Low Sensing-Time VLSI-Architecture of MED based Spectrum Sensor for Cognitive Radio,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, May-2019, Japan (Sapporo) web link.

Rahul Shrestha, Pooja Bansal and Srikant Srinivasan, “High-Throughput and High-Speed Polar-Decoder VLSI-Architecture for 5G New Radio,” 32nd IEEE International Conference on VLSI Design and 18th International Conference on Embedded Systems (VLSID), pp. 329-334, January-2019 web link.

Sweeta Ghosh, Vikram Thakur, Rahul Shrestha, Vinayak Hande, Shubhajit Roy Chowdhury, “Design and Simulation of Low Cost and Low Magnetic Field MRI System,” 12th International Conference on Sensor Technologies and Applications (SENSORCOMM), pp. 31-36, September-2018, Italy (Venice) web link.

Rahul Shrestha and Ashutosh Sharma, “VLSI-Architecture of Radix-2/4/8 SISO Decoder for Turbo Decoding at Multiple Data-rates,” 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp. 131-136, October-2018, Italy (Verona), web link.

Rohit Chaurasiya, John Gustafson, Rahul Shrestha, Jonathan Neudorfer, Sangeeth Nambiar, Kaustav Niyogi, Farhad Merchant, Rainer Leupers, “Parameterized Posit Arithmetic Hardware Generator,” 36th IEEE International Conference on Computer Design (ICCD), pp. 334-341, October-2018, USA (Orlando, Florida), web link.

Rahul Shrestha and Ashutosh Sharma, “Reconfigurable VLSI-Architecture of Multi-Radix Maximum-A-Posteriori Decoder for New Generation of Wireless Devices,” 22nd IEEE International Symposium on VLSI Design and Test (VDAT), pp. 37-48, June-2018, web link.

Mahesh S. Murty and Rahul Shrestha, “Hardware-Efficient and Wide-Band Frequency-Domain Energy Detector for Cognitive-RadioWireless Network,” 31st IEEE International Conference on VLSI Design and 17th International Conference on Embedded Systems (VLSID), pp. 277-282, January-2018, web link.

Dinesh Kumar B., Sumit Pandey, Puneet Arora and Rahul Shrestha, “A Self-Bandwidth Switching & Area-Efficient PLL Using Multiplexer-Controlled Frequency Selector,” 7th IEEE International Symposium on Embedded Computing and System Design (ISED), pp. 1-5, December-2017, web link.

Rahul Kurzekar, Hardik Arora and Rahul Shrestha, “Embedded Hardware Prototype for Gas Detection and Monitoring System in Android Mobile Platform,” 3rd IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), pp. 6-10, December-2017, web link.

Sumanth Gudaparthi and Rahul Shrestha, “Energy-Efficient VLSI Architecture & Implementation of Bi-Modal Multi-Banked Register-File Organization,” 21st IEEE International Symposium on VLSI Design and Test (VDAT), pp. 299-312, December-2017, web link.

Naman Govil, Rahul Shrestha and Shubhajit Roy Chowdhury, “A New Multi-Objective Hardware-Software-Partitioning Algorithmic Approach for High Speed Applications,” 21st IEEE International Symposium on VLSI Design and Test (VDAT), pp. 62-68, December-2017, web link.

Rahul Shrestha, “High-Speed and Low-Power VLSI-Architecture for Inexact Speculative Adder,” IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), pp. 1-4, April-2017, Taiwan (Hsinchu), web link.

Enna Sachdeva, Pratik Porwal, Nalini Vidyulatha and Rahul Shrestha, “Design of Low power VLSI-Architecture and ASIC Implementation of Fuzzy Logic based Automatic Car-Parking System,” 13th International IEEE India Conference (INDICON), pp. 1-6, December-2016, web link.

Soumitr Sanjay Dubey, Rahul Shrestha and Shubhajit Roy Chowdhury, “A Novel Architecture for Computing Eigenvalues of Matrix for High Speed Applications,” 13th International IEEE India Conference (INDICON), pp. 1-5, December-2016, web link.

Lalit Kumar, Deepak Kumar Mittal and Rahul Shrestha, “VLSI-Design and FPGA-Implementation of GMSK-Demodulator Architecture Using CORDIC Engine for Low-Power Application,” 13th International IEEE India Conference (INDICON), pp. 1-6, December-2016 (Best Poster Awarded), web link.

Gayatri Nair, Swathi Ramasahayam, Rahul Shrestha and Shubhajit Roy Chowdhury, “Non-Invasive Estimation of Blood Parameters from Composite Signal Using Near Infrared Spectroscopy Coupled with Independent Component Analysis,” 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), August-2016, USA (Orlando), web link.

Rahul Shrestha, Vinay Swargam and Mahesh S. Murty, “Cognitive-Radio Wireless-Sensor Based on Energy Detection with Improved Accuracy: Performance and Hardware Perspectives,” 20th IEEE International Symposium on VLSI Design and Test (VDAT), pp. 1-6, December-2016, web link.

Mahesh S. Murty and Rahul Shrestha, “VLSI Architecture for Cyclostationary Feature Detection based Spectrum Sensing for Cognitive-Radio Wireless Networks and Its ASIC Implementation,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 69-74, July-2016, USA (Pittsburgh), web link.

Rahul Shrestha and Utkarsh Rastogi, “Design and Implementation of Area-Efficient and Low-Power Configurable Booth-Multiplier,” 29th IEEE International Conference on VLSI Design and the 15th International Conference on Embedded Systems (VLSID), pp. 599-600, January-2016, web link.

Rahul Shrestha and Roy Paily, “Hardware Implementation and Testing of Log-MAPP Decoder Based on Novel Un-Grouped Sliding-Window Technique,” 5th IEEE International Symposium on Electronics System Design (ISED), pp. 171-175, 2014. (Best Paper Awarded), web link.

Vijaya Kumar K, Rahul Shrestha and Roy Paily, “Design and Implementation of Multi-Rate LDPC Decoder for IEEE 802.16e Wireless Standard,” IEEE International Conference on Green Computing, Communication and Electrical Engineering (ICGCCEE), pp. 1-5, 2014, web link.

Rahul Shrestha and Roy Paily, “System Level Hardware Testing of a High Speed MAP Decoder Implemented on FPGA,” IEEE International Conference on Signal Processing, Computing and Control (ISPCC), pp. 1-6, 2013, web link.

Rahul Shrestha and Roy Paily, “A Novel State Metric Normalization Technique for High-Throughput Maximum-a-Posteriori-Probability Decoder,” IEEE International Conference on Advances in Computing, Communications and Informatics (ICACCI), pp. 903-907, 2013, web link.

Rahul Shrestha and Roy Paily, “Design and Implementation of a High Speed MAP Decoder Architecture for Turbo Decoding,” 26th IEEE International Conference on VLSI Design and the 12th International Conference on Embedded Systems (VLSID), pp. 86-91, 2013, web link.

Rahul Shrestha and Roy Paily, “Design and Data Width Requirement for Fixed Point Turbo Decoders Based on Modified MAP algorithm,” IEEE International Conference on Signal Processing and Communications (SPCOM), pp. 1-5, 2012, web link.

Rahul Shrestha and Roy Paily, “Hardware Implementation of Max-Log-MAP Algorithm Based on Maclaurin Series for Turbo Decoder,” IEEE International Conference on Communications and Signal Processing (ICCSP), pp. 509-511, 2011, web link.