DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd"> Dr. Hitesh Shrimali<< IIT Mandi

Dr. Hitesh Shrimali

Phone : +91-(1905)267-902
EMail : hitesh@iitmandi.ac.in
Address : School of Computing and Electrical Engineering
A10-403, North Campus
School of Computing and electrical Engineering
Kamand Campus, IIT Mandi
Mandi, Himachal Pradesh -- 175005
India

Bio-sketch

    I am an associate professor in the school of computing and electrical engineering. Before joining IIT Mandi, I did B.E. from Nirma Institute of Technology (Ahmedabad), M.Tech. from IIT Kharagpur and Ph.D. from IIT Delhi. My M.Tech. and Ph.D. theses were under the guidance of Prof. Amit Patra and Dr. Shouri Chatterjee respectively. After that I joined STMicroelectronics (Greater Noida) as a senior design engineer. After having 2 years of industrial experience, I worked with Università degli Studi di Milano as a post doctorate researcher, under the guidance of Prof. Valentino Liberali. During post-doctorate experience, I was also associated with INFN [Istituto Nazionale di Fisica Nucleare] Milano.

Research interests

  • Design and testing of radiation hard circuits [CMOS silicon detectors]
  • Analog and mixed signal VLSI design [ADCs]
  • Modeling of radiation effects on analog and mixed signal circuits
  • On-chip Instrumentation

Chip tape-outs at IIT Mandi

From left-to-right: 1. high voltage high resistive front-end electronics for particle detection application in ST 180nm BCD Technology (collaboration with University of Milan, and INFN Milan), 2. EEG front end circuit in SCL 180nm CMOS Technology, 3. Low Noise Instrumentation Amplifier for sensor application in SCL 180nm CMOS Technology, 4. Two Hybrid flash-SAR ADCs, reduced switching based ADC, and frequency synthesiser(130nm UMC).

Workshop

Honours and Awards

  • All-Rounder Contribution Award for the Execution of Academic and Research Activities at IIT Mandi (2017);
  • Distinguished Alumni Award 2017 (Nirma University)
  • Recipient of Young Faculty Research Fellowship (YFRF), MeitY, Govt. of India.

Work Experience

  • Associate Professor: Indian Institute of Technology Mandi [Jun'19 -- present]
  • Assistant Professor: Indian Institute of Technology Mandi [Dec'14 -- May'19]
  • Post Doctorate Researcher: Università degli Studi di Milano [Jun'13 -- Dec'14]
  • Senior Design Engineer: STMicroelectronics, Greater Noida [Aug'11 - Jun'13]

On-going sponsored research projects

  • Project: Young Faculty Research Fellowship
  • Funding Agency: Ministry of Electronics and Technology (MeitY), Govt. of India ( Role: PI)
    Sanctioned Amount: 1,480,000 INR
  • Project: Special Man-power Development project from Chip to system design (SMDP-C2SD)
  • Funding Agency: Ministry of Electronics and Technology (MeitY), Govt. of India ( Role: PI)
    Sanctioned Amount: 6,038,000 INR
  • Project: Design and Fabrication of Interface ASIC for Vibratory Gyroscope Sensor Application
  • Funding Agency: Indian Space Research Organization (ISRO), Govt. of India ( Role: Co-PI)
    Sanctioned Amount: 4,500,000 INR
  • Seed grant project
  • Funding Agency: Indian Institute of Technology Mandi ( Role: PI)
    Sanctioned Amount: 6,50,000 INR

Academic Administrative Experience

    Present duties

  • Chair, Curriculum review committee for BTech (EE)
  • Chief Election Officer (2020)
  • Chair, Student Affairs Panel (SAP), IIT Mandi [Dec'19 - present]
  • Course coordinator, M. Tech. (VLSI), IIT Mandi [Aug'18 - Present]
  • Advisor, Art Geeks, IIT Mandi [Dec'19 - present]
  • Past duties

  • Advisor, Science and Technology Councill, IIT Mandi [Apr'16-Dec'19]
  • Faculty Advisor, Bech. (EE), 2015-batch, IIT Mandi [Agu'15-Jun'19]
  • Co-advisor, Career and Placement Cell, IIT Mandi [Apr'16 - Jun'18]
  • Faculty advisor, M. Tech. (VLSI), 2016-batch, IIT Mandi [Aug'16 - Jun'18]
  • Course coordinator, M. Tech. (VLSI), IIT Mandi [Aug'16 - Sept'17]
  • Event Advisor, Inter IIT Tech Meet 2016
  • Advisor, Robotronics Club, IIT Mandi [Apr'16 - present]
  • Advisor, Electronics Club, IIT Mandi [Mar'15 - Apr'16]
  • Advisor, IEEE IES IIT Mandi student chapter (Aug'15 - Apr'16),
  • Co-advisor, Cultural Club, IIT Mandi [Mar'15 - Apr'16]

Students and project staffs

PhD students (Institute Scholars)

    1. Saurabh Dhiman (May'19 to present)

PhD students under DeitY Visweswaraya fellowship

    1. Vijender Sharma (Feb'16 to present -- with co-supervision of Dr. Jai Narayan Tripathi, IIT Jodhpur)
    2. Kumar Sambhav Pandey (Feb'17 to present)

PhD student under SMDP-C2SD project

    1. Dinesh Kumar B. (Feb'17 to present)

SMDP-C2SD Project Staff

  • Dinesh Kumar B.: Project Engineer (Mar'16 to present)
  • Vivek Thakur (Oct'19 to present)
  • Vivek Kumar: Project Associae (Mar'18 to Apr'19)
  • Ankita Deo: Project Associate (Jan'17 to Dec'17)
  • Sonal: Project Associate (Mar'16 to Dec'16)

Theses guidance

    Graduate Students

      1. Saurabh Trivedi (MTech in VLSI, Jul'20-present) -- Intern at Cadence
      2. Shubham Saxena (MTech in VLSI, Jul'20-present) -- Intern at STMicroelectronics
      3. Shivam (MTech in VLSI, Jul'20-present) -- Intern at STMicroelectronics
      4. Gowtham PK (MTech in VLSI, Jul'20-present) -- Intern at STMicroelectronics
      5. Osho Gera (MTech in VLSI, Jul'20-present) -- Intern at STMicroelectronics
      6. Adarsh Ahlawat (MTech in VLSI, May'29-present)--Intern at NXP

Graduated students

    Doctor of Philosophy (PhD)

      1. Dr. Shivani Sharma [Jan'15-Jul'20]
      2. Dr. Ashish Joshi [Jan'15-Jun'20]
      3. Dr. Indu Yadav [Feb'15-May'20]

    M.Tech. in VLSI

      1. Sandeep Pareek (MTech in VLSI, May'19-Jul'20) -- Design Engineer at NXP-Semiconductor
      2. Saswat (MTech in VLSI, May'19-Jul'20) -- Design Engineer at Cadence, Pune
      3. Monu Mehta (M.Sc. in Physics, Jun'19-Jul'20)
      4. Suhail Illikkal (MTech in VLSI, May'18-Jul'19) -- Design Engineer at Cadence, Noida
      5. Vartika Verma (MTech in VLSI, May'18-Jul'19) -- Design Engineer at NXP semiconductor, Noida
      6. Rupal Jain (MTech in VLSI, May'18-Jun'19)
      7. Sumit Kumar Pandey (MTech in VLSI, May'17-Jun'18) -- Senior ASIC Designer at Western Digital, Bangalore
      8. Puneet Arora (MTech in VLSI, May'17-Jun'18) -- Design Engineer at Synopsys, Noida

    B.Tech.

      1. Piyush Patil (BTech in EE, Jul'19-Jul'20) -- Software Engineer, Marvel Semiconductor
      2. Rachit Maheshwari (BTech in EE, Jul'19-Jul'20) -- Software Engineer, Canadian Global Informatics
      3. Himanshu Kumar (BTech in EE, Jul'18-Jun'19) -- OLX, Bangalore
      4. Nitesh Bansiwal (BTech in EE, Jul'17-Jun'18) -- Decision Analytics Associate, ZX Associates, Pune
      5. Anubhav Agrawal (BTech in EE, Jul'17-Jun'18) -- Associate Product Manager, OLX, Bngalore
      6. Anurag Rakde (BTech in EE, Jul'17-Jun'18) -- Design Engineer at Qualcomm, Hyderabad
      7. Niraj Singh (B.Tech. EE - 2016)
      8. Rohit Raghav (B.Tech. EE - 2016)

Teaching

  • [Feb-Jun 2020]: EE211 -- Analog Circuit Design
  • [Feb-Jun 2019 and Aug-Dec 2019]: EE203 -- Network Theory
  • [Feb-Jun 2019]: EE519P -- CMOS Digital IC Design Practicum
  • [Feb-Jun 2016, 2018 and 2019]: EE619 -- Mixed Signal VLSI Design
  • [Feb-Jun 2015 and Aug-Dec of 2015 to 2019]: EE512 -- CMOS Analog IC design
  • [Aug-Dec 2015, 2016 and 2017]: DP504P -- Electrical and Mechanical Workshop (for M. Sc. students)
  • [Feb-Jun 2015, 2016 and 2017]: IC161 -- Applied Electronics
  • [Feb-Jun 2015, 2016 and 2017]: IC161P -- Applied Electronics laboratory
  • [Feb-Jun 2015, 2016 and 2017]: IC201P -- Design Practicum (Mentor for two groups)

On-line Video Lectures

Delivered Video Lectures

  • A lecture on, "Design and Modeling of Energy Efficient Hybrid Flash-SAR ADC" (Aug. 22, 2020) (Slides)
  • FDP on "Trends towards Industry 4.0 in Mixeds Signal SOCs" for JUIT, Solan, HP (June 17, 2020)
  • On-chip Power Delivery Networks for IIT Jodhpur (Link to the Lecture)
  • High speed CMOS analog IC design for IIIT Gwalior (Apr'18)
  • BJT, MOSFET and amplifiers; frequency response for QEEE phase 9 (Feb'18)
  • Linear integrated circuits -- design with opamp for QEEE phase 8(Sep'17)
  • Differential amplifiers for QEEE phase 7 (Mar.'17)
  • BJT/MOS amplifier for QEEE phase 6 (Feb'16)

Activities

  • Fellowship Chair: IEEE VDAT conference 2019
  • Organising committee member: IEEE EDAPS conference 2018

Research Publications

Patents

  1. A. Joshi, H. Shrimali , S.K. Sharma, "Reconfigurable Reduced Switching Activity (Rsw) Mode for an Analog-To-Digital Converter", Indian patent, application number 201911042977, filed in Oct. 2019.
  2. U. Kunwar, P. Chaturvedi, H. Shrimali, "Fully automated electrostatic page turning technique and device for document scanning", Indian patent application number 201911044970, filed in Nov. 2019.

Peer Reviewed International Journals

  1. A. Joshi, H. Shrimali and S. K. Sharma, "A Discrete-Time MOS Parametric Amplifier based Chopped Signal Demodulator" in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Aug. 2020 (Early Access). IEEExplore link (DOI: 10.1109/TVLSI.2020.3015947)
  2. V.K. Sharma, J. N. Tripathi, and H. Shrimali , "Deterministic Noise Analysis in Single-Stage Amplifiers by Extension of Indefinite Admittance Matrix", in IEEE Open Journal of Circuits and Systems (OJCAS), Aug. 2020 (Early Access). IEEExplore_link (DOI: 10.1109/OJCAS.2020.3016017)
  3. A. Joshi, H. Shrimali and S. K. Sharma, "Reduced Switching Mode for a SAR ADC: Analysis and Design of a SAR A-to-D Algorithm with Periodic Stand-by Mode Circuit Components" in IET Circuits, Devices & Systems, Vol. 14, issue 5, Aug. 2020, pp. 686-694. IEEExplore link (DOI: 10.1049/iet-cds.2019.0224)
  4. D. Kumar, S.K. Pandey, N. Gupta and H. Shrimali "Design of hybrid flash-SAR ADC using an inverter based comparator in 28 nm CMOS" in Elsevier Microelectronics, vol. 95, Jan. 2020, 104666.Elsevier_Link (DOI: 10.1016/j.mejo.2019.104666)
  5. J.N. Tripathi, S. Illikkal, H. Shrimali, R. Achar, "A Thomas Algorithm based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers", in IEEE Access, vol. 7, Jul. 2019, pp. 125240-125252.IEEExplore_link (DOI: 10.1109/ACCESS.2019.2937922)
  6. I. Yadav, H. Shrimali , "Noise and Crosstalk Models of the Particle Detector with Zero-Pole Transformation Charge Sensitive Amplifier", in Elsevier Nuclear Instruments and Methods in Physics Research: A, Vol. 937, 1 Sept. 2019, pp. 107-116. Elsevier_Link (DOI: 10.1016/j.nima.2019.05.037)
  7. S. Sharma, S. Das, R. Khosla, H. Shrimali and S. K. Sharma, "Realization and Performance Analysis of Facile Processed µ-IDE based multi-layer HfS2/HfO2 Transistors" in IEEE Transaction on Electron Devices, vol. 66, no. 7, Jul. 2019, pp. 3236-3241. IEEExplore_link (DOI: 10.1109/TED.2019.2917323)
  8. S. Sharma, S. Das, R. Khosla, H. Shrimali and S. K. Sharma, "Highly UV sensitive Sn Nanoparticles blended with polyaniline onto Micro-Interdigitated Electrode Array for UV-C detection applications" in Journal of Materials Science: Materials in Electronics, Vol. 30, Issue 8, Apr. 2019, pp 7534-7542. Read Paper (DOI: 10.1007/s10854-019-01067-9)
  9. J.N. Tripathi, P. Arora, H. Shrimali and R. Achar, "Efficient Jitter Analysis for a Chain of CMOS Inverters", in IEEE Transactions on Electromagnetic Compatibility, vol. 10, Oct. 2018, pp. 1-11. IEEExplore_link (DOI: 10.1109/TEMC.2018.2878354)
  10. J.N. Tripathi, V. Sharma and H. Shrimali , "A Review on Power Supply Induced Jitter", in IEEE Transactions on Components, Packaging and Manufacturing Technology (TCPMT), vol. 9, issue 3, Sept. 2018, pp. 511 - 524. IEEExplore_link (DOI: 10.1109/TCPMT.2018.2872608)
  11. S. Sharma, S. Das, H. Shrimali and S. K. Sharma, "High-Performance CSA-PANI based Organic Phototransistor by Elastomer Gratings" in Elsevier Journal of Organic Electronics, Vol. 57, pp. 14-20, Jun. 2018, pp. 14-20. ElsevierLink (DOI: 10.1016/j.orgel.2018.02.031)
  12. I. Yadav, H. Shrimali , A.Andreazza, V. Liberali, "Analytical Expressions for Noise and Crosstalk Voltages of the High Energy Silicon Particle Detector", Journal of Instrumentation, Institute of Physics (IOP) science, vol. 13, Jan. 2018, pg. C01019. IOP_Link (DOI: 10.1088/1748-0221/13/01/c01019)
  13. S. Sharma, R. Khosla, D. Deva, H. Shrimali and S. K. Sharma, "Fluorine-chlorine co-doped TiO2/CSA doped polyaniline based high performance inorganic/organic hybrid heterostructure for UV photodetection applications" in Elsevier Sensors & Actuators: A. physical, vol. 261, Jul. 2017, pp. 94-102. Elsevier_link (DOI: 10.1016/j.sna.2017.04.043)
  14. A. Joshi, H. Shrimali and S. K. Sharma, "A Systematic Design Approach for a Gain Boosted Telescopic OTA with Cross Coupled Capacitor" in IET Circuits, Devices & Systems, Vol. 11, issue 3, Jun. 2017, pp. 225 - 231. IEEExplore_link (DOI: 10.1049/iet-cds.2016.0448)
  15. A. Andreazza, A. Castoldi, V. Ceriale, G. Chiodini, M. Citterio, G. Darbo, G. Gariano, A. Gaudiello, C. Guazzoni, A. Joshi, V. Liberali, S. Passadore, F. Ragusa, E. Ruscino, C. Sbarra, A. Sidoti, H. Shrimali, A. Stabile, I. Yadav and E. Zaffaroni, "HV-CMOS detectors in BCD8 technology", Journal of Instrumentation, Institute of Physics (IOP) science, vol. 11, Nov. 2016, pp. C11038.IOP_Link (DOI: 10.1088/1748-0221/11/11/c11038)
  16. H. Shrimali and Shouri Chatterjee, "A Technique to Linearize the Discrete-Time Parametric Amplifier and its Variants," Elsevier Microelectronics Journal, vol. 46, no. 11, Nov 2015, pp. 1033-1038.Elsevier_Link (DOI: 10.1016/j.mejo.2015.08.013)
  17. H. Shrimali and V. Liberali, "Parametric Amplifier based Dynamic clocked Comparator," Elsevier Solid State Electronics, vol. 101, Nov. 2014, pp. 85-89. Elsevier_Link (DOI: 10.1016/j.sse.2014.06.043)
  18. A. Camplani, S. Shojaii, H. Shrimali, V Liberali, “CMOS IC Radiation Hardening by Design”, in FACTA Universitatis, Journal series: Electronics and Energetics Vol. 27, no. 2, June 2014, pp.251–258. Read Paper (DOI: 10.2298/FUEE1402251C)
  19. H. Shrimali and S. Chatterjee, "Distortion analysis of a three terminal MOS-based discrete time parametric amplifier," in IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 58 , No. 12, Dec. 2011, pp. 902-905. IEEExplore_link (DOI: 10.1109/TCSII.2011.2172710)

Peer Reviewed International Conferences

  1. V.K. Sharma, J.N. Tripathi, H. Shrimali, "An Inspection Based Method to Analyse Deterministic Noise in N-port Circuits", in the IEEE EPEPS 2020 (accepted).
  2. V.K. Sharma, J.N. Tripathi, H. Shrimali, "A Generalized Approach for Analyzing the Impact of Supply Noise in MOS Amplifiers", in the IEEE SPI 2020 (accepted).
  3. S. Dhiman, V.K. Sharma, H. Shrimali,"Design and Analysis of Low PSIJ, Energy Efficient Bootstrapped Driver for Space Application", in the IEEE ISCAS, Oct. 2020, Seville, Spain (accepted).
  4. I. Yadav, A. Joshi, E. Ruscino, V. Liberali, A.Andrezza, H. Shrimali, "Design of HV-CMOS Detectors in BCD Technology with Noise and Crosstalk Measurements", in the IEEE ICECS, Nov. 2019, Genova, Italy. IEEExplore link (DOI: 10.1109/ICECS46596.2019.8965094)
  5. S. Dhiman, I. Yadav, H. Shrimali,"Energy Efficient Bootstrapped Driver for a Particle Detector in 180 nm SOI Technology", in the Asia Pacific Conference on Circuits and Systems (APCCAS) 2019, Bangkok, Thailand. IEEExplore link (DOI: 10.1109/APCCAS47518.2019.8953075)
  6. K. S. Pandey, Dinesh B., N. Goel, H. Shrimali , "An Ultra-Fast Parallel Prefix Adder" in the IEEE Computer Arithmetic (Arith), Kyoto, Japan, Jun. 10-12, 2019. IEEExplore link (DOI: 10.1109/ARITH.2019.00034)
  7. S. Illikkal, J. Tripathi, H. Shrimali , "Jitter Estimation in a CMOS Tapered Buffer for an Application of Clock Distribution Network" in the IEEE APEMC, Sapporo, Japan, Jun. 3-7, 2019. IEEExplore link (DOI: 10.23919/EMCTokyo.2019.8893857)
  8. V.K. Sharma, Dinesh B., S. Illikkal, J.N. Tripathi, N. Gupta, H. Shrimali, "Analysis of Timing Error Due to Supply and Substrate Noise in an Inverter Based High-Speed Comparator", in the IEEE ISCAS, Sapporo, Japan, May. 2019. IEEExplore link (DOI: 10.1109/ISCAS.2019.8702313)
  9. Dinesh B., N. Gupta, H. Shrimali, "A 6-Bit 29.56 fJ/conv-Step, Voltage Scalable Flash-SAR Hybrid ADC in 28 nm CMOS", in the IEEE ISCAS, Sapporo, Japan, May. 2019. IEEExplore link (DOI: 10.1109/ISCAS.2019.8702482)
  10. S. Illikkal, J. Tripathi, H. Shrimali , "Analyzing the Impact of Various Deterministic Noise Sources on Jitter in a CMOS Inverter" in the IEEE International Conference on Signal Processing & Integrated Networks, SPIN 2019, Delhi, Mar. 7-8, 2019.IEEExplore link (DOI: 10.1109/SPIN.2019.8711770)
  11. I. Yadav, A. Joshi, E. Ruscino, A. Andreazza, V. Liberali, H. Shrimali , "Design of a Charge Sensitive Amplifier for Silicon Particle Detector in BCD 180 nm Process" in the International Conference on VLSI Design (VLSID), Delhi, India, Jan. 5-9, 2019. IEEExplore link (DOI: 10.1109/VLSID.2019.00126)
  12. V.Sharma, J. Tripathi, H. Shrimali , "Extension of EMPSIJ Method for Substrate Noise Induced Jitter: an Inverter Case Study" in the IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Symposium, Chandigarh, India, Dec. 16-18, 2018. IEEExplore link (DOI: 10.1109/EDAPS.2018.8680885)
  13. V.Sharma, J. Tripathi, H. Shrimali , "A Quick Assessment of Nonlinearity in Power Delivery Networks" in the IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Symposium, Chandigarh, India, Dec. 16-18, 2018. IEEExplore link (DOI: 10.1109/EDAPS.2018.8680881)
  14. A. Deo, S.K. Pandey, A. Joshi, S.K. Sharma, H. Shrimali, "Design of a Third Order Butterworth Gm-C Filter for EEG Signal Detection Application", in IEEE International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), Gdynia, Poland, Jun. 21-23, 2018. IEEExplore link (DOI: 10.23919/MIXDES.2018.8436689)
  15. A. Joshi, H. Shrimali , S.K. Sharma, "The Capacitively Coupled Chopper Stabilized Amplifier With a DTPA based Demodulator", in IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, May. 27-30, 2018, pp-1-5. IEEExplore link (DOI: 10.1109/ISCAS.2018.8351188)
  16. H. Shrimali , V.Sharma, J. Tripathi, R. Malik, "Nonlinear Modeling and Analysis of Buck Converter using Volterra Series" in IEEE International Conference on Electronics Circuits and Systems (ICECS), Batumi, Georgia, Dec. 5-8, 2017, pp-222-226. IEEExplore link (DOI: 10.1109/ICECS.2017.8292119)
  17. V.Sharma, J. Tripathi, H. Shrimali , R. Malik, "The Harmonics Impact Study of a DC-DC Buck Converter through a Power Delivery Network" in the IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Symposium, Hangzhou, China, Dec. 14-16, 2017, pp-1-3. IEEExplore link (DOI: 10.1109/EDAPS.2017.8276952)
  18. Dinesh Kumar B., H. Shrimali , "Design of a 520 μW, –141 dBc/Hz and 450 MHz Frequency Synthesizer using Low Power and Low Phase Noise Current Reuse VCO" in IEEE TENCON, Penang, Malaysia, Nov 5-8, 2017, pp-2937-2912. IEEExplore link (DOI: 10.1109/TENCON.2017.8228365)
  19. V.Sharma, H. Shrimali , J. Tripathi, R. Malik, "Distortion Analysis for a DC-DC Buck Converter" in the International SoC design conference (ISOCC), Seoul, Korea, Nov 5-8, 2017, pp-212-213 (Got the ISOCC Best Paper Award). IEEExplore link (DOI: 10.1109/ISOCC.2017.8368857)
  20. H. Shrimali , A. Joshi, E. Ruscino, I. Yadav, S. K. Sharma, A. Andreazza, V. Liberali, "Design of a Charge Sensitive Amplifier for Particle Detection Application in BCD 180~nm Technology" in the International Workshops on Radiation Imaging Detectors (iWoRid), Krakow, Poland, July 2-6, 2017.
  21. I. Yadav, H. Shrimali , A.Andreazza, V. Liberali, "Analytical Expressions for Noise and Crosstalk Voltages of the High Energy Silicon Particle Detector" in the International Workshops on Radiation Imaging Detectors (iWoRid), Krakow, Poland, July 2-6, 2017.
  22. A. Andreazza, A. Castoldi, V. Ceriale, G. Chiodini, M. Citterio, G. Darbo, G. Gariano, A. Gaudiello, C. Guazzoni, V. Liberali, S. Passadore, F. Ragusa, A. Rovani, E. Ruscino, C. Sbarra, H. Shrimali and E. Zaffaroni, "HV-CMOS detectors for High Energy Physics: characterization of BCD8 technology and controlled hybridization technique" in IEEE Nuclear Science Symposium 2016 (NSS), Oct. 29- Nov. 6, 2016, pp-1-3. IEEExplore link (DOI: 10.1109/NSSMIC.2016.8069868)
  23. A. Joshi, I. Yadav, S. Sharma, H. Shrimali , "The Pole-zero Doublet: a Cascode Operational Amplifier with Cross Coupled Capacitor" in IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Abu Dhabi (UAE), Oct. 16-19, 2016, pp-1-4. IEEExplore link (DOI: 10.1109/MWSCAS.2016.7869985)
  24. A. Andreazza, A. Castoldi, V. Ceriale, G. Chiodini, M. Citterio, G. Darbo, G. Gariano, A. Gaudiello, C. Guazzoni, V. Liberali, S. Passadore, F. Ragusa, A. Rovani, E. Ruscino, C. Sbarra, H. Shrimali and E. Zaffaroni, "Characterization of HV-CMOS detectors in BCD8 technology and of a controlled hybridization technique", in the International Workshop on Vertex Detectors, Vertex 2016, Isola d'Elba, Italy, Sept. 25-30, 2016.
  25. A. Andreazza, A. Castoldi, G. Chiodini, M. Citterio, G. Darbo, G. Gariano, A. Gaudiello, C. Guazzoni, A. Joshi, V. Liberali, S. Passadore, F. Ragusa, E. Ruscino, C. Sbarra, A. Sidoti, H. Shrimali, I. Yadav and E. Zaffaroni, "HV-CMOS detectors in BCD8 technology", in the International Workshop on Semiconductor Pixel Detectors for Particles and Imaging (Pixel 2016), Sestri Levante, Italy, Sept. 5-9, 2016.
  26. A. Andreazza, A. Castoldi, G. Chiodini, M. Citterio, G. Darbo, G. Gariano, A. Gaudiello, C. Guazzoni, V. Liberali, S. Passadore, F. Ragusa, A. Rovani, E. Ruscino, C. Sbarra, A. Sidoti, H. Shrimali and E. Zaffaroni, "HV-CMOS detectors for High Energy Physics: characterization of BCD8 technology and controlled hybridization technique", in the International Workshops on Radiation Imaging Detectors (iWoRid), Barcelona, Spain, July 3-7, 2016.
  27. J. Tripathi, V. Sharma, H. Advani, P. Singh, H. Shrimali and R. Malik, "An Analysis of Power Supply Induced Jitter for a Voltage Mode Driver in High Speed Serial Links", in IEEE Workshop on Signal and Power Integrity (SPI), Turin, Italy, May 8-11, 2016, pp-1-4. IEEExplore link (DOI: 10.1109/SaPIW.2016.7496259)
  28. H. Shrimali and V. Liberali, "The Start-up Circuit for a Low Voltage Bandgap Reference", in IEEE International Conference on Electronics Circuits and Systems (ICECS), Marseille, France, Dec 7-10, 2014, pp-92-95. IEEExplore link (DOI: 10.1109/ICECS.2014.7049929)
  29. H. Shrimali and V. Liberali, "A Threshold Voltage Modeling for A Spacer-Trapping Memory Cell Using Verilog-A," in Workshop on Compact Modeling (WCM), Washington, USA, June 16-18, 2014, pp-529-532.Paper_link (ISBN: 978-1-4822-5827-1)
  30. H. Shrimali, “Discrete Time Parametric Amplifier based Dynamic clocked Comparator” in International Semiconductor Device Research Symposium (ISDRS) 2013, Bethesda (Maryland), Dec. 10-13, 2013.Paper_link
  31. H. Shrimali and S. Chatterjee, "Third order harmonic cancellation technique for a parametric amplifier," in IEEE International Symposium on Circuits and Systems (ISCAS), Rio de Janeiro, Brazil, May 15-18, 2011, pp. 1880–1883. IEEExplore link (DOI: 10.1109/ISCAS.2011.5937954)
  32. H. Shrimali and S. Chatterjee, "11 GHz UGBW Op-amp with feed-forward compensation technique," in IEEE International Symposium on Circuits and Systems (ISCAS), Rio de Janeiro, Brazil, May 15-18, 2011, pp. 17–20. IEEExplore link (DOI: 10.1109/ISCAS.2011.5937490)

Poster Presentations

  1. V.K. Sharma, J.N. Tripathi, and H. Shrimali, "Moedling and analysis of power delivery network using Volterra series" Poster presented at PhD Forum, VLSI-SOC 2018, Verona, Italy, 2018.
  2. H. Shrimali, "Third order harmonic cancellation technique for a parametric amplifier," Poster presented on National science day, Indian Institute of Technology Delhi, Feb 28, 2011.
  3. H. Shrimali, "Ultra low power high speed on­chip digital storage oscilloscope," Poster presented on National science day, Indian Institute of Technology Delhi, Feb 29, 2008.
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