Dr. Hitesh Shrimali

Phone : +91-(1905)267-902
EMail : hitesh@iitmandi.ac.in
Address : School of Computing and Electrical Engineering
A10-403, North Campus
School of Computing and electrical Engineering
Kamand Campus, IIT Mandi
Mandi, Himachal Pradesh -- 175005
India

Bio-sketch

    I am an associate professor in the school of computing and electrical engineering. Before joining IIT Mandi, I did B.E. from Nirma Institute of Technology (Ahmedabad), M.Tech. from IIT Kharagpur and Ph.D. from IIT Delhi. My M.Tech. and Ph.D. theses were under the guidance of Prof. Amit Patra and Dr. Shouri Chatterjee respectively. After that I joined STMicroelectronics (Greater Noida) as a senior design engineer. After having 2 years of industrial experience, I worked with Università degli Studi di Milano as a post doctorate researcher, under the guidance of Prof. Valentino Liberali. During post-doctorate experience, I was also associated with INFN [Istituto Nazionale di Fisica Nucleare] Milano.

Research interests

  • Design and testing of radiation hard circuits [CMOS silicon detectors]
  • Analog and mixed signal VLSI design [ADCs]
  • Modeling of radiation effects on analog and mixed signal circuits
  • On-chip Instrumentation

Chip tape-outs at IIT Mandi

From left-to-right: 1. high voltage high resistive front-end electronics for particle detection application in ST 180nm BCD Technology (collaboration with University of Milan, and INFN Milan), 2. EEG front end circuit in SCL 180nm CMOS Technology, 3. Low Noise Instrumentation Amplifier for sensor application in SCL 180nm CMOS Technology, 4. Two Hybrid flash-SAR ADCs, reduced switching based ADC, and frequency synthesiser(130nm UMC).

Workshop

Honours and Awards

  • "Excellent and Consistent Teaching Performance Combined with Contributions Towards Institute Services" on the 12th Foundation Day of IIT Mandi (February 24, 2021)
  • "All-Rounder Contribution Award for the Execution of Academic and Research Activities" on the 8th Foundation Day of IIT Mandi (February 24, 2017);
  • "Distinguished Alumni Award -- 2017" (Nirma University)
  • "Recipient of Young Faculty Research Fellowship (YFRF)", MeitY, Govt. of India

Work Experience

  • Associate Professor: Indian Institute of Technology Mandi [Jun'19 -- present]
  • Assistant Professor: Indian Institute of Technology Mandi [Dec'14 -- May'19]
  • Post Doctorate Researcher: Università degli Studi di Milano [Jun'13 -- Dec'14]
  • Senior Design Engineer: STMicroelectronics, Greater Noida [Aug'11 - Jun'13]

On-going sponsored research projects

    1. Design and fabrication of an interface ASIC for a vibratory gyroscope sensor application
    2. Funding agency: ISRO, Department of Space ( Role: PI)
      Sanctioned Amount: 32,29,000/- INR
    3. Design of high-speed ADC for a high speed transceiver srchitectures
    4. Funding agency: DST-DAAD ( Role: PI)
      Sanctioned Amount: 5,43,025 INR
    5. Project: VLSI Chip Designing Research (Young Faculty Research Fellowship)
    6. Funding Agency: Ministry of Electronics and Technology (MeitY), Govt. of India ( Role: PI)
      Sanctioned Amount: 37,00,000 INR
    7. Project: Learning Engineering through Activity Program (LEAP) ( Role: Co-PI)
    8. Functional under IITM incubation cell on behalf of IIT Madras
      Funding Agency: Maker Bhavan Foundation, A Charitable Foundation incorporated in the USA for enabling Science Technology Engineering and Math Education and Research in India
      Sanctioned Amount: 1,00,00,000 INR
    9. Project: Design and Fabrication of Interface ASIC for Vibratory Gyroscope Sensor Application
    10. Funding Agency: Indian Space Research Organization (ISRO), Govt. of India ( Role: Co-PI)
      Sanctioned Amount: 45,00,000 INR

Completed research projects

    1. Project: Special Man-power Development project from Chip to system design (SMDP-C2SD)
    2. Funding Agency: Ministry of Electronics and Technology (MeitY), Govt. of India ( Role: PI)
      Sanctioned Amount: 62,00,000 INR (Dec. 2015 to Nov. 2021)
    3. Seed grant project
    4. Funding Agency: Indian Institute of Technology Mandi ( Role: PI)
      Sanctioned Amount: 6,50,000 INR

Academic Administrative Experience

    Present duties

    1. Coordinator, IP and TT Cell, IIT Mandi (Jan'22 to present)
    2. Chair, BTech IC-PFG, IIT Mandi (Aug'21 to present)
    3. Nodal Officer, Visweswaraya PhD Scheme, MeitY (Jun. 2021 to present)
    4. Chair, SCEE Publicity Committee (Mar. 2021 to present)
    5. Chair, Curriculum review committee for BTech (EE) (Nov. 2020 to present)
    6. Chair, Campus Return [CaRe] Committee (Oct. 2020 to present)
    7. Chair, Student Affairs Panel (SAP), IIT Mandi [Dec'19 - present]
    8. Past duties

      1. Chief Election Officer, Gymkhana, IIT Mandi (Jun. 2020, and Jun. 2021)
      2. Course coordinator, M. Tech. (VLSI), IIT Mandi [Aug'18 - Aug'21]
      3. Advisor, Art Geeks, IIT Mandi [Dec'19 - Aug'21]
      4. Advisor, Science and Technology Councill, IIT Mandi [Apr'16-Dec'19]
      5. Faculty Advisor, Bech. (EE), 2015-batch, IIT Mandi [Agu'15-Jun'19]
      6. Co-advisor, Career and Placement Cell, IIT Mandi [Apr'16 - Jun'18]
      7. Faculty advisor, M. Tech. (VLSI), 2016-batch, IIT Mandi [Aug'16 - Jun'18]
      8. Course coordinator, M. Tech. (VLSI), IIT Mandi [Aug'16 - Sept'17]
      9. Event Advisor, Inter IIT Tech Meet 2016
      10. Advisor, Robotronics Club, IIT Mandi [Apr'16 - present]
      11. Advisor, Electronics Club, IIT Mandi [Mar'15 - Apr'16]
      12. Advisor, IEEE IES IIT Mandi student chapter (Aug'15 - Apr'16),
      13. Co-advisor, Cultural Club, IIT Mandi [Mar'15 - Apr'16]

Students and project staffs

PhD students (Institute Scholars)

    1. Vikash Singh (Feb'22 to present)
    2. Saurabh Dhiman (May'19 to present)

PhD student under SMDP-C2SD project

    1. Dinesh Kumar B. (Feb'17 to present)

Part-time PhD students

    1. Aishwarya Kumari (Feb'21 to present) -- Cadence pvt. ltd., Bangalore, India
    2. Kumar Sambhav Pandey (Feb'17 to present) -- NIT Hamirpur

Master of Science (MS) by Research students

    1. Sowmyashree S. (Sep'21 to present)

SMDP-C2SD Project Staff

  • Dinesh Kumar B.: Project Engineer (Mar'16 to present)
  • Vivek Thakur: Project Assocaite (Oct'19 to May'21)
  • Vivek Kumar: Project Associae (Mar'18 to Apr'19)
  • Ankita Deo: Project Associate (Jan'17 to Dec'17)
  • Sonal: Project Associate (Mar'16 to Dec'16)

Theses guidance

    Graduate Students

      1. Nishanth Kumar (MTech in VLSI, Jul'21-present) -- Intern at Intel
      2. Bharath Mohan (MTech in VLSI, Jul'21-present) -- Intern at Intel
      3. Chaitnya Anand (MTech in VLSI, Jul'21-present) in Co-guidance with Dr. Srikanth Sugavanam
      4. Deepank Yadav (MTech in VLSI, Jul'21-present) -- Intern at Intel, in co-guidance with Dr. Satinder Kumar Sharma

    Under graduate students

      1. Sudhanshu Chauhan (BTech in EE, Jul'19-present) -- Intern at SSPL, DRDO
      2. Srinivas Khatavkar (BTech in EE, Jul'19-present) -- Intern at SSPL, DRDO

Graduated students

    Doctor of Philosophy (PhD)

      1. Dr. Vijender Kumar Sharma (Feb'16 to Oct'21) -- Synopsys, Noida
      2. Dr. Shivani Sharma [Jan'15-Jul'20] -- Asst. Prof., KIET, UPTU, India
      3. Dr. Ashish Joshi [Jan'15-Jun'20] -- Intel, Bangalore, India
      4. Dr. Indu Yadav [Feb'15-May'20] -- Siemens EDA, Noida

    Graduate Students

      1. Saurabh Trivedi (MTech in VLSI, Jul'20-Jun'21) -- Cadence, Bangalore
      2. Shubham Saxena (MTech in VLSI, Jul'20-Jun'21) -- Cadence, Noida
      3. Shivam (MTech in VLSI, Jul'20-Jun'21) -- Electricity Board, Haryana Govt.
      4. Gowtham PK (MTech in VLSI, Jul'20-Jun'21) -- Cadence, Noida
      5. Osho Gera (MTech in VLSI, Jul'20-Jun'21) -- NVIDIA, Bangalore
      6. Devrishi (MTech in VLSI, Jul'20-Jul'21) -- TI, Bangalore
      7. Sandeep Pareek (MTech in VLSI, May'19-Jul'20) -- Design Engineer at NXP-Semiconductor
      8. Saswat (MTech in VLSI, May'19-Jul'20) -- Design Engineer at Cadence, Pune
      9. Monu Mehta (M.Sc. in Physics, Jun'19-Jul'20)
      10. Adarsh Ahlawat (MTech in VLSI, May'19-Dec'20)
      11. Suhail Illikkal (MTech in VLSI, May'18-Jul'19) -- Design Engineer at Cadence, Noida
      12. Vartika Verma (MTech in VLSI, May'18-Jul'19) -- PhD at TU-Munich
      13. Rupal Jain (MTech in VLSI, May'18-Jun'19)
      14. Alvendra Singh (MTech in VLSI, May'18-Jun'19) -- Section Engineer, Indian Railways, Jaipur, India
      15. Sumit Kumar Pandey (MTech in VLSI, May'17-Jun'18) -- Senior ASIC Designer at Western Digital, Bangalore
      16. Puneet Arora (MTech in VLSI, May'17-Jun'18) -- Design Engineer at STMicroelectronics, Greater Noida

    Under-graduate Students

      1. Piyush Patil (BTech in EE, Jul'19-Jul'20) -- Component Engineer, Intel pvt. ltd., India
      2. Rachit Maheshwari (BTech in EE, Jul'19-Jul'20) -- Software Engineer, Canadian Global Informatics
      3. Himanshu Kumar (BTech in EE, Jul'18-Jun'19) -- OLX, Bangalore
      4. Nitesh Bansiwal (BTech in EE, Jul'17-Jun'18) -- Decision Analytics Associate, ZX Associates, Pune
      5. Anubhav Agrawal (BTech in EE, Jul'17-Jun'18) -- Associate Product Manager, OLX, Bngalore
      6. Anurag Rakde (BTech in EE, Jul'17-Jun'18) -- Design Engineer at Qualcomm, Hyderabad
      7. Niraj Singh (B.Tech. EE - 2016)
      8. Rohit Raghav (B.Tech. EE - 2016)

Teaching

  • [Aug-Dec 2021] IC101P -- Reverse Engineering (Co-cordinator)
  • [Feb-Jun 2021] IC201P -- Design Practicum (Co-coordinator)
  • [Aug-Dec 2020, 2021] EE524-- Digital MOS LSI Circuits
  • [Feb-Jun 2020] EE211 -- Analog Circuit Design
  • [Feb-Jun 2019 and Aug-Dec 2019]: EE203 -- Network Theory
  • [Feb-Jun 2019, 2021] EE519P -- CMOS Digital IC Design Practicum
  • [Feb-Jun 2016, 2018 and 2019]: EE619 -- Mixed Signal VLSI Design
  • [Feb-Jun 2015 and Aug-Dec of 2015 to 2019]: EE512 -- CMOS Analog IC design
  • [Aug-Dec 2015, 2016, 2017, 2022]: DP504P -- Electrical and Mechanical Workshop (for M. Sc. students)
  • [Feb-Jun 2015, 2016 and 2017]: IC161 -- Applied Electronics
  • [Feb-Jun 2015, 2016 and 2017]: IC161P -- Applied Electronics laboratory

On-line Video Lectures

Invited Lectures

  • A lecture on “VLSI: Growing Opportunities with the Shrinking Technology Node” for the BTech first year Orientation of IIIT-Una, HP, Dec. 18, 2021,
  • A lecture on “Design Methodology: Reverse to Forward Engineering Approach” for ATAL FDP on Design Thinking: From Insights to Viability for Engineers, Dec. 9, 2021.
  • Webinar series on Analog and mixed-signal VLSI design for Vignan's Foundation for Science, Technology and Research, AP, India (Jun. 16, 2021)
  • AICTE sponsored Short Term Training Program (STTP) on Mixed Signal Design approaches for Artificial Intelligence Processors for LBRCE, AP, India (March 2021)
  • A lecture on, "Design and Modeling of Energy Efficient Hybrid Flash-SAR ADC", for NIT Jalandhar (Aug. 22, 2020) (Slides)
  • FDP on "Trends towards Industry 4.0 in Mixeds Signal SOCs" for JUIT, Solan, HP (June 17, 2020)
  • On-chip Power Delivery Networks for IIT Jodhpur (Link to the Lecture)
  • High speed CMOS analog IC design for IIIT Gwalior (Apr'18)
  • BJT, MOSFET and amplifiers; frequency response for QEEE phase 9 (Feb'18)
  • Linear integrated circuits -- design with opamp for QEEE phase 8(Sep'17)
  • Differential amplifiers for QEEE phase 7 (Mar.'17)
  • BJT/MOS amplifier for QEEE phase 6 (Feb'16)

Activities

  • Review Editor: Frontiers in Electronics -- Intergrated Circuits and VLSI
  • Fellowship Chair: IEEE VDAT conference 2019
  • Organising committee member: IEEE EDAPS conference 2018

Patents

  1. S. Dhiman, N. Gupta, and H. Shrimali , "Method of running an unrolled binary search or multiple level search for pipeline ADC", Application number: 202013054196, filed in Mar. 2022.
  2. Dinesh B., N. Gupta, and H. Shrimali , "Adaptive hybrid analog-to-digital converter with fractional/multi bit per cycle conversion", Application number: 202013054196, filed in Dec. 2020.
  3. Dinesh B., N. Gupta, and H. Shrimali , "Hybrid analog-to-digital converter with fractional/multi bit per cycle conversion", application number 202011053662, filed in Dec. 2020.
  4. A. Joshi, H. Shrimali , S.K. Sharma, "Reconfigurable Reduced Switching Activity (Rsw) Mode for an Analog-To-Digital Converter", application number 201911042977, filed in Oct. 2019.
  5. U. Kunwar, P. Chaturvedi, H. Shrimali, "Fully automated electrostatic page turning technique and device for document scanning", application number 201911044970, filed in Nov. 2019.

Peer Reviewed International Journals

    2022

    1. V.K. Sharma, J.N. Tripathi, H. Shrimali, "Design and Distortion Analysis of a Power Delivery Network in the Presence of Internal Supply Noise", in IEEE Transactions on Components, Packaging and Manufacturing Technology (TCPMT), impact factor: 1.738 (Accepted in May 2022)
    2. D. Balasubramanian, H. Shrimali,"Design and Implementation of a Second Order PLL based Frequency Synthesizer for Implantable Medical Devices", in Elsevier: Integration the VLSI Journal (Accepted), impact factor: 1.211.
    3. K.S. Pandey, H. Shrimali, "Novel VLSI Architectures and Micro-cell Libraries for Subscalar Computations", in IEEE Access, IEEE_link (DOI: 10.1109/ACCESS.2022.3157879) impact factor: 3.367.

    2021

    1. V.K. Sharma, J.N. Tripathi, H. Shrimali, "Analysis of Power Supply Noise in AMS Circuits including the effects of Interconnects using Estimation", Elsevier AEUE - International Journal of Electronics and Communications, Vol. 139, Sept. 2021, pp. 153913, Elsevier_link (DOI: https://doi.org/10.1016/j.aeue.2021.153913) impact factor: 3.183.
    2. A. Joshi, H. Shrimali and S. K. Sharma, "Digitally Assisted Secondary Switch-and-Compare Technique for a SAR ADC", in IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), vol. 68, issue 7, pp. 2317-2321, Jul. 2021, IEEExplore link (DOI: 10.1109/TCSII.2021.3053210) impact factor: 2.814
    3. P. Arora, J.N. Tripathi, H. Shrimali , "A Device Parameters based Analytical Modeling of Power Supply Induced Jitter in CMOS Inverters", in IEEE Transactions on Electron Devices (TED), IEEExplore link, pp. 3268-3275, vol. 68, issue 7, Jul. 2021 (DOI: 10.1109/TED.2021.3082106) impact factor: 2.913
    4. N. Gupta, A. Makosiej, H. Shrimali, A. Amara, A. Vladimirescu, C. Anghel, "Tunnel FET Negative-Differential-Resistance Based 1T1C Refresh-Free-DRAM, 2T1C SRAM and 3T1C DRAM", in IEEE Transactions on Nanotechnology, vol. 20, pp. 270-227, Feb. 2021, IEEExplore link (DOI: 10.1109/TNANO.2021.3061607) impact factor: 2.857.

    2020

    1. A. Joshi, H. Shrimali and S. K. Sharma, "A Discrete-Time MOS Parametric Amplifier based Chopped Signal Demodulator" in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 28, no. 11, pp. 2268-2279, Nov. 2020. IEEExplore link (DOI: 10.1109/TVLSI.2020.3015947) impact factor: 2.037
    2. V.K. Sharma, J. N. Tripathi, and H. Shrimali , "Deterministic Noise Analysis in Single-Stage Amplifiers by Extension of Indefinite Admittance Matrix", in IEEE Open Journal of Circuits and Systems (OJCAS), vol. 1, pp. 124-139, 2020. IEEExplore_link (DOI: 10.1109/OJCAS.2020.3016017)
    3. A. Joshi, H. Shrimali and S. K. Sharma, "Reduced Switching Mode for a SAR ADC: Analysis and Design of a SAR A-to-D Algorithm with Periodic Stand-by Mode Circuit Components" in IET Circuits, Devices & Systems, Vol. 14, issue 5, Aug. 2020, pp. 686-694. IEEExplore link (DOI: 10.1049/iet-cds.2019.0224) impact factor: 1.277
    4. Dinesh B., S.K. Pandey, N. Gupta and H. Shrimali "Design of hybrid flash-SAR ADC using an inverter based comparator in 28 nm CMOS" in Microelectronics Journal, vol. 95, Jan. 2020, 104666.Elsevier_Link (DOI: 10.1016/j.mejo.2019.104666) impact factor: 1.405

    2019

    1. J.N. Tripathi, S. Illikkal, H. Shrimali, R. Achar, "A Thomas Algorithm based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers", in IEEE Access, vol. 7, Jul. 2019, pp. 125240-125252.IEEExplore_link (DOI: 10.1109/ACCESS.2019.2937922) impact factor: 3.745
    2. I. Yadav, H. Shrimali , "Noise and Crosstalk Models of the Particle Detector with Zero-Pole Transformation Charge Sensitive Amplifier", in Elsevier Nuclear Instruments and Methods in Physics Research: A, Vol. 937, 1 Sept. 2019, pp. 107-116. Elsevier_Link (DOI: 10.1016/j.nima.2019.05.037) impact factor: 1.265
    3. S. Sharma, S. Das, R. Khosla, H. Shrimali and S. K. Sharma, "Realization and Performance Analysis of Facile Processed µ-IDE based multi-layer HfS2/HfO2 Transistors" in IEEE Transaction on Electron Devices, vol. 66, no. 7, Jul. 2019, pp. 3236-3241. IEEExplore_link (DOI: 10.1109/TED.2019.2917323) impact factor: 2.913
    4. S. Sharma, S. Das, R. Khosla, H. Shrimali and S. K. Sharma, "Highly UV sensitive Sn Nanoparticles blended with polyaniline onto Micro-Interdigitated Electrode Array for UV-C detection applications" in Journal of Materials Science: Materials in Electronics, Vol. 30, Issue 8, Apr. 2019, pp 7534-7542. Read Paper (DOI: 10.1007/s10854-019-01067-9) impact factor: 2.220

    2018

    1. J.N. Tripathi, P. Arora, H. Shrimali and R. Achar, "Efficient Jitter Analysis for a Chain of CMOS Inverters", in IEEE Transactions on Electromagnetic Compatibility, vol. 10, Oct. 2018, pp. 1-11. IEEExplore_link (DOI: 10.1109/TEMC.2018.2878354)impact factor: 1.882
    2. J.N. Tripathi, V. Sharma and H. Shrimali , "A Review on Power Supply Induced Jitter", in IEEE Transactions on Components, Packaging and Manufacturing Technology (TCPMT), vol. 9, issue 3, Sept. 2018, pp. 511 - 524. IEEExplore_link (DOI: 10.1109/TCPMT.2018.2872608) impact factor: 1.889
    3. S. Sharma, S. Das, H. Shrimali and S. K. Sharma, "High-Performance CSA-PANI based Organic Phototransistor by Elastomer Gratings" in Elsevier Journal of Organic Electronics, Vol. 57, pp. 14-20, Jun. 2018, pp. 14-20. ElsevierLink (DOI: 10.1016/j.orgel.2018.02.031) impact factor: 3.31
    4. I. Yadav, H. Shrimali , A.Andreazza, V. Liberali, "Analytical Expressions for Noise and Crosstalk Voltages of the High Energy Silicon Particle Detector", Journal of Instrumentation, Institute of Physics (IOP) science, vol. 13, Jan. 2018, pg. C01019. IOP_Link (DOI: 10.1088/1748-0221/13/01/c01019) impact factor: 1.454

    2017

    1. S. Sharma, R. Khosla, D. Deva, H. Shrimali and S. K. Sharma, "Fluorine-chlorine co-doped TiO2/CSA doped polyaniline based high performance inorganic/organic hybrid heterostructure for UV photodetection applications" in Elsevier Sensors & Actuators: A. physical, vol. 261, Jul. 2017, pp. 94-102. Elsevier_link (DOI: 10.1016/j.sna.2017.04.043) impact factor: 2.904
    2. A. Joshi, H. Shrimali and S. K. Sharma, "A Systematic Design Approach for a Gain Boosted Telescopic OTA with Cross Coupled Capacitor" in IET Circuits, Devices & Systems, Vol. 11, issue 3, Jun. 2017, pp. 225 - 231. IEEExplore_link (DOI: 10.1049/iet-cds.2016.0448) impact factor: 1.277

    2016

    1. A. Andreazza, A. Castoldi, V. Ceriale, G. Chiodini, M. Citterio, G. Darbo, G. Gariano, A. Gaudiello, C. Guazzoni, A. Joshi, V. Liberali, S. Passadore, F. Ragusa, E. Ruscino, C. Sbarra, A. Sidoti, H. Shrimali, A. Stabile, I. Yadav and E. Zaffaroni, "HV-CMOS detectors in BCD8 technology", Journal of Instrumentation, Institute of Physics (IOP) science, vol. 11, Nov. 2016, pp. C11038.IOP_Link (DOI: 10.1088/1748-0221/11/11/c11038) impact factor: 1.454

    2015

    1. H. Shrimali and Shouri Chatterjee, "A Technique to Linearize the Discrete-Time Parametric Amplifier and its Variants," Microelectronics Journal, vol. 46, no. 11, Nov 2015, pp. 1033-1038.Elsevier_Link (DOI: 10.1016/j.mejo.2015.08.013) impact factor: 1.405

    2014

    1. H. Shrimali and V. Liberali, "Parametric Amplifier based Dynamic clocked Comparator," Solid State Electronics Journal, vol. 101, Nov. 2014, pp. 85-89. Elsevier_Link (DOI: 10.1016/j.sse.2014.06.043) impact factor: 1.437
    2. A. Camplani, S. Shojaii, H. Shrimali, V Liberali, “CMOS IC Radiation Hardening by Design”, in FACTA Universitatis, Journal series: Electronics and Energetics Vol. 27, no. 2, June 2014, pp.251–258. Read Paper (DOI: 10.2298/FUEE1402251C) impact factor: 0.515

    2011

    1. H. Shrimali and S. Chatterjee, "Distortion analysis of a three terminal MOS-based discrete time parametric amplifier," in IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 58 , No. 12, Dec. 2011, pp. 902-905. IEEExplore_link (DOI: 10.1109/TCSII.2011.2172710) impact factor: 2.814

Peer Reviewed International Conferences

    2021

    1. G.P. Kalarikkal, R. Goel, H. Shrimali, "Design of CMOS Device Process Sensor in 28 nm FD-SOI with 2 % of Frequency Spread", in the IEEE ICECS, Dubai, UAE, pp. 1-6, IEEExplorer link (DOI: 10.1109/ICECS53924.2021.9665465).
    2. N. Gupta,H. Shrimali, A. Makosiej, A. Vladimirescu, A. Amara, "Energy Efficient Comparator-Less Current-Mode TFET-CMOS Co-Integrated Scalable Flash ADC", in IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Aug. 2021, pp. 297-300, IEEExplorer link (DOI: 10.1109/MWSCAS47672.2021.9531911).
    3. P. Arora, J.N. Tripathi, H. Shrimali, "Analytical Modeling of Jitter in CMOS Inverters Due to Periodic Fluctuations in Power Supply", in IEEE NEWCAS, June 2021, pp. 1-4, IEEExplorer link (DOI: 10.1109/NEWCAS50681.2021.9462738).
    4. Dinesh B., H. Shrimali, N. Nallam, "A Low-Power Quadrature LC− Oscillator Using Core-and-Coupling Current-Reuse", in IEEE ISCAS, pp. 1-5, May 2021, IEEExplorer link (DOI: 10.1109/ISCAS51556.2021.9401110).

    2020

    1. V.K. Sharma, J.N. Tripathi, H. Shrimali, "An Inspection Based Method to Analyse Deterministic Noise in N-port Circuits", in the IEEE EPEPS 2020, pp-1-3, Oct. 2020.IEEExplorer link (DOI: 10.1109/EPEPS48591.2020.9231394)
    2. V.K. Sharma, J.N. Tripathi, H. Shrimali, "A Generalized Approach for Analyzing the Impact of Supply Noise in MOS Amplifiers", in the IEEE SPI 2020, pp- 1-4, May. 2020.IEEExplore link (DOI: 10.1109/SPI48784.2020.9218158)
    3. S. Dhiman, V.K. Sharma, H. Shrimali,"Design and Analysis of Low PSIJ, Energy Efficient Bootstrapped Driver for Space Application", in the IEEE ISCAS, Oct. 2020, Seville, Spain.IEEExplore link (DOI:10.1109/ISCAS45731.2020.9181133)

    2019

    1. I. Yadav, A. Joshi, E. Ruscino, V. Liberali, A.Andrezza, H. Shrimali, "Design of HV-CMOS Detectors in BCD Technology with Noise and Crosstalk Measurements", in the IEEE ICECS, Nov. 2019, Genova, Italy. IEEExplore link (DOI: 10.1109/ICECS46596.2019.8965094)
    2. S. Dhiman, I. Yadav, H. Shrimali,"Energy Efficient Bootstrapped Driver for a Particle Detector in 180 nm SOI Technology", in the Asia Pacific Conference on Circuits and Systems (APCCAS) 2019, Bangkok, Thailand. IEEExplore link (DOI: 10.1109/APCCAS47518.2019.8953075)
    3. K. S. Pandey, Dinesh B., N. Goel, H. Shrimali , "An Ultra-Fast Parallel Prefix Adder" in the IEEE Computer Arithmetic (Arith), Kyoto, Japan, Jun. 10-12, 2019. IEEExplore link (DOI: 10.1109/ARITH.2019.00034)
    4. S. Illikkal, J. Tripathi, H. Shrimali , "Jitter Estimation in a CMOS Tapered Buffer for an Application of Clock Distribution Network" in the IEEE APEMC, Sapporo, Japan, Jun. 3-7, 2019. IEEExplore link (DOI: 10.23919/EMCTokyo.2019.8893857)
    5. V.K. Sharma, Dinesh B., S. Illikkal, J.N. Tripathi, N. Gupta, H. Shrimali, "Analysis of Timing Error Due to Supply and Substrate Noise in an Inverter Based High-Speed Comparator", in the IEEE ISCAS, Sapporo, Japan, May. 2019. IEEExplore link (DOI: 10.1109/ISCAS.2019.8702313)
    6. Dinesh B., N. Gupta, H. Shrimali, "A 6-Bit 29.56 fJ/conv-Step, Voltage Scalable Flash-SAR Hybrid ADC in 28 nm CMOS", in the IEEE ISCAS, Sapporo, Japan, May. 2019. IEEExplore link (DOI: 10.1109/ISCAS.2019.8702482)
    7. S. Illikkal, J. Tripathi, H. Shrimali , "Analyzing the Impact of Various Deterministic Noise Sources on Jitter in a CMOS Inverter" in the IEEE International Conference on Signal Processing & Integrated Networks, SPIN 2019, Delhi, Mar. 7-8, 2019.IEEExplore link (DOI: 10.1109/SPIN.2019.8711770)
    8. I. Yadav, A. Joshi, E. Ruscino, A. Andreazza, V. Liberali, H. Shrimali , "Design of a Charge Sensitive Amplifier for Silicon Particle Detector in BCD 180 nm Process" in the International Conference on VLSI Design (VLSID), Delhi, India, Jan. 5-9, 2019. IEEExplore link (DOI: 10.1109/VLSID.2019.00126)

    2018

    1. V.Sharma, J. Tripathi, H. Shrimali , "Extension of EMPSIJ Method for Substrate Noise Induced Jitter: an Inverter Case Study" in the IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Symposium, Chandigarh, India, Dec. 16-18, 2018. IEEExplore link (DOI: 10.1109/EDAPS.2018.8680885)
    2. V.Sharma, J. Tripathi, H. Shrimali , "A Quick Assessment of Nonlinearity in Power Delivery Networks" in the IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Symposium, Chandigarh, India, Dec. 16-18, 2018. IEEExplore link (DOI: 10.1109/EDAPS.2018.8680881)
    3. A. Deo, S.K. Pandey, A. Joshi, S.K. Sharma, H. Shrimali, "Design of a Third Order Butterworth Gm-C Filter for EEG Signal Detection Application", in IEEE International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), Gdynia, Poland, Jun. 21-23, 2018. IEEExplore link (DOI: 10.23919/MIXDES.2018.8436689)
    4. A. Joshi, H. Shrimali , S.K. Sharma, "The Capacitively Coupled Chopper Stabilized Amplifier With a DTPA based Demodulator", in IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, May. 27-30, 2018, pp-1-5. IEEExplore link (DOI: 10.1109/ISCAS.2018.8351188)

    2017

    1. H. Shrimali , V.Sharma, J. Tripathi, R. Malik, "Nonlinear Modeling and Analysis of Buck Converter using Volterra Series" in IEEE International Conference on Electronics Circuits and Systems (ICECS), Batumi, Georgia, Dec. 5-8, 2017, pp-222-226. IEEExplore link (DOI: 10.1109/ICECS.2017.8292119)
    2. V.Sharma, J. Tripathi, H. Shrimali , R. Malik, "The Harmonics Impact Study of a DC-DC Buck Converter through a Power Delivery Network" in the IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Symposium, Hangzhou, China, Dec. 14-16, 2017, pp-1-3. IEEExplore link (DOI: 10.1109/EDAPS.2017.8276952)
    3. Dinesh Kumar B., H. Shrimali , "Design of a 520 μW, –141 dBc/Hz and 450 MHz Frequency Synthesizer using Low Power and Low Phase Noise Current Reuse VCO" in IEEE TENCON, Penang, Malaysia, Nov 5-8, 2017, pp-2937-2912. IEEExplore link (DOI: 10.1109/TENCON.2017.8228365)
    4. V.Sharma, H. Shrimali , J. Tripathi, R. Malik, "Distortion Analysis for a DC-DC Buck Converter" in the International SoC design conference (ISOCC), Seoul, Korea, Nov 5-8, 2017, pp-212-213 (Got the ISOCC Best Paper Award). IEEExplore link (DOI: 10.1109/ISOCC.2017.8368857)

    2016

    1. A. Andreazza, A. Castoldi, V. Ceriale, G. Chiodini, M. Citterio, G. Darbo, G. Gariano, A. Gaudiello, C. Guazzoni, V. Liberali, S. Passadore, F. Ragusa, A. Rovani, E. Ruscino, C. Sbarra, H. Shrimali and E. Zaffaroni, "HV-CMOS detectors for High Energy Physics: characterization of BCD8 technology and controlled hybridization technique" in IEEE Nuclear Science Symposium 2016 (NSS), Oct. 29- Nov. 6, 2016, pp-1-3. IEEExplore link (DOI: 10.1109/NSSMIC.2016.8069868)
    2. A. Joshi, I. Yadav, S. Sharma, H. Shrimali , "The Pole-zero Doublet: a Cascode Operational Amplifier with Cross Coupled Capacitor" in IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Abu Dhabi (UAE), Oct. 16-19, 2016, pp-1-4. IEEExplore link (DOI: 10.1109/MWSCAS.2016.7869985)
    3. J. Tripathi, V. Sharma, H. Advani, P. Singh, H. Shrimali and R. Malik, "An Analysis of Power Supply Induced Jitter for a Voltage Mode Driver in High Speed Serial Links", in IEEE Workshop on Signal and Power Integrity (SPI), Turin, Italy, May 8-11, 2016, pp-1-4. IEEExplore link (DOI: 10.1109/SaPIW.2016.7496259)

    2014

    1. H. Shrimali and V. Liberali, "The Start-up Circuit for a Low Voltage Bandgap Reference", in IEEE International Conference on Electronics Circuits and Systems (ICECS), Marseille, France, Dec 7-10, 2014, pp-92-95. IEEExplore link (DOI: 10.1109/ICECS.2014.7049929)
    2. H. Shrimali and V. Liberali, "A Threshold Voltage Modeling for A Spacer-Trapping Memory Cell Using Verilog-A," in Workshop on Compact Modeling (WCM), Washington, USA, June 16-18, 2014, pp-529-532.Paper_link (ISBN: 978-1-4822-5827-1)

    2013

    1. H. Shrimali, “Discrete Time Parametric Amplifier based Dynamic clocked Comparator” in International Semiconductor Device Research Symposium (ISDRS) 2013, Bethesda (Maryland), Dec. 10-13, 2013.Paper_link

    2011

    1. H. Shrimali and S. Chatterjee, "Third order harmonic cancellation technique for a parametric amplifier," in IEEE International Symposium on Circuits and Systems (ISCAS), Rio de Janeiro, Brazil, May 15-18, 2011, pp. 1880–1883. IEEExplore link (DOI: 10.1109/ISCAS.2011.5937954)
    2. H. Shrimali and S. Chatterjee, "11 GHz UGBW Op-amp with feed-forward compensation technique," in IEEE International Symposium on Circuits and Systems (ISCAS), Rio de Janeiro, Brazil, May 15-18, 2011, pp. 17–20. IEEExplore link (DOI: 10.1109/ISCAS.2011.5937490)

Posters

  1. V.K. Sharma, J.N. Tripathi, and H. Shrimali, "Modeling and analysis of power delivery network using Volterra series" Poster presented at PhD Forum, VLSI-SOC 2018, Verona, Italy, 2018.
  2. H. Shrimali , A. Joshi, E. Ruscino, I. Yadav, S. K. Sharma, A. Andreazza, V. Liberali, "Design of a Charge Sensitive Amplifier for Particle Detection Application in BCD 180~nm Technology" in the International Workshops on Radiation Imaging Detectors (iWoRid), Krakow, Poland, July 2-6, 2017.
  3. I. Yadav, H. Shrimali , A.Andreazza, V. Liberali, "Analytical Expressions for Noise and Crosstalk Voltages of the High Energy Silicon Particle Detector" in the International Workshops on Radiation Imaging Detectors (iWoRid), Krakow, Poland, July 2-6, 2017.
  4. A. Andreazza, A. Castoldi, V. Ceriale, G. Chiodini, M. Citterio, G. Darbo, G. Gariano, A. Gaudiello, C. Guazzoni, V. Liberali, S. Passadore, F. Ragusa, A. Rovani, E. Ruscino, C. Sbarra, H. Shrimali and E. Zaffaroni, "Characterization of HV-CMOS detectors in BCD8 technology and of a controlled hybridization technique", in the International Workshop on Vertex Detectors, Vertex 2016, Isola d'Elba, Italy, Sept. 25-30, 2016.
  5. A. Andreazza, A. Castoldi, G. Chiodini, M. Citterio, G. Darbo, G. Gariano, A. Gaudiello, C. Guazzoni, A. Joshi, V. Liberali, S. Passadore, F. Ragusa, E. Ruscino, C. Sbarra, A. Sidoti, H. Shrimali, I. Yadav and E. Zaffaroni, "HV-CMOS detectors in BCD8 technology", in the International Workshop on Semiconductor Pixel Detectors for Particles and Imaging (Pixel 2016), Sestri Levante, Italy, Sept. 5-9, 2016.
  6. A. Andreazza, A. Castoldi, G. Chiodini, M. Citterio, G. Darbo, G. Gariano, A. Gaudiello, C. Guazzoni, V. Liberali, S. Passadore, F. Ragusa, A. Rovani, E. Ruscino, C. Sbarra, A. Sidoti, H. Shrimali and E. Zaffaroni, "HV-CMOS detectors for High Energy Physics: characterization of BCD8 technology and controlled hybridization technique", in the International Workshops on Radiation Imaging Detectors (iWoRid), Barcelona, Spain, July 3-7, 2016.
  7. H. Shrimali, "Third order harmonic cancellation technique for a parametric amplifier," Poster presented on National science day, Indian Institute of Technology Delhi, Feb 28, 2011.
  8. H. Shrimali, "Ultra low power high speed on­chip digital storage oscilloscope," Poster presented on National science day, Indian Institute of Technology Delhi, Feb 29, 2008.
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